This application claims the benefits of U.S. Provisional Application No. 63/074,270, filed September 3, 2020, and U.S. Provisional Application No. 63/074,296, filed September 3, 2020. The entire contents of both applications are incorporated by reference incorporated herein in their entirety.
This disclosure pertains to integrated circuits (ICs) that control power to electronic devices over the Universal Serial Bus (USB).
Various electronic devices (e.g. smartphones, tablets, notebooks, laptops, chargers, adapters, power banks, etc.) are configured to transfer power through USB ports according to USB power delivery protocols, which are available in different versions and revisions defined by the USB Power Delivery (USB-PD) specification. For example, in some applications, an electronic device can be configured as a power consumer that receives power from a USB port (for example, to charge the battery), while in other applications, an electronic device can be configured as a power source to provide power. another device Power device connected to it through a USB port. In various applications, electronics manufacturers may also use power converters (e.g., buck-boost converters) that must meet various USB PD specification requirements, such as output voltage (Vout), monotonicity, and stability requirements.
The following description contains numerous specific details such as examples of specific systems, components, methods, etc. to provide a thorough understanding of various implementations of the USB Type-C controller mode transition architecture described herein. However, it will be apparent to those skilled in the art that at least some embodiments can be practiced without these specific details. In other cases, known components, elements, or methods are not described in detail or are presented in a simple block diagram to avoid unnecessarily obscuring the topic being described. Therefore, the specific details set forth below are examples only. Certain implementations may differ from these exemplary details and still be considered within the spirit and scope of the present embodiments.
References in the specification to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and "various embodiments" mean that a particular feature, structure, step, operation, or specific feature described in connection with that embodiment (s) is included in at least one embodiment. In addition, the terms "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", and "various embodiments" in the specification do not necessarily refer to the same embodiment(s). ).
The description includes references to the accompanying drawings, which form part of the detailed description. The drawings show representations according to exemplary embodiments. These embodiments, which may also be referred to herein as "examples", are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The performances may be combined, other performances may be used, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the subject matter claimed. It is to be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable any person skilled in the art to practice, make and/or use the subject matter.
Describes various embodiments of a mode transition architecture in USB Type-C controllers that can be deployed to operate in various electronic devices. Examples of such electronic devices include, but are not limited to, personal computers (e.g., laptops, notebooks, etc.), mobile computing devices (e.g., tablets, tablet computers, e-readers, etc.), mobile communications devices (e.g., smartphones, mobile phones, personal digital assistants, messaging devices, pocket PCs, etc.), connectivity and charging devices (e.g. cables, hubs, docking stations, adapters, chargers, etc.), audio/video/data recording and/or playback devices (e.g. cameras, voice recorders, handheld scanners, monitors, etc.) and other similar electronic devices that may use USB interfaces for communication, battery charging, and/or power.
As used herein, "USB-compatible" device or system refers to a device or system that contains a USB connection interface, is configured with, or is otherwise connected to a USB connection interface. A USB-compatible electronic device can conform to at least one version of a Universal Serial Bus (USB) specification. Examples of such USB specifications include, but are not limited to, the USB Revision 2.0 specification, the USB 3.0 specification, the USB 3.1 specification, the USB 3.2 specification and/or various amendments, versions and errata thereof. The USB specifications generally define the characteristics (e.g., attributes, protocol definition, transaction types, bus management, programming interfaces, etc.) of a differential serial bus necessary for designing and building standard communications systems and peripherals. For example, a USB-compatible peripheral device is connected to a USB-compatible host device through a USB port of the host device to form a USB-compatible system. A USB 2.0 port contains a 5V power line (labeled VBUS), a differential pair of data lines (labeled D+ or DP and D− or DN), and a power return ground line (labeled GND). A USB 3.0 connector also provides the VBUS, D+, D−, and GND lines for backward compatibility with USB 2.0. To support a faster differential bus (the USB SuperSpeed bus), a USB 3.0 port also provides a differential pair of transmitter data lines (labeled SSTX+ and SSTX−) and a differential pair of receiver data lines (labeled SSRX+ and SSRX−), a power line for power (also referred to as DPWR) and a power return ground (also referred to as DGND). A USB 3.1 port provides the same lines as a USB 3.0 port for backward compatibility with USB 2.0 and USB 3.0 communications, but improves SuperSpeed bus performance with a suite of features known as Enhanced SuperSpeed.
A newer USB connector technology called USB Type-C (also referred to herein as "USB-C") is defined in various versions and/or revisions of the USB Type-C specification. The USB Type-C specification defines Type-C connectors, Type-C plugs and Type-C cables that can support both USB communication and power delivery over newer USB power delivery protocols available in different revisions/versions of the USB PD specification are defined. Examples of USB Type-C capabilities and requirements include USB 2.0 and USB 3.0/3.1 data and other communications, electromechanical definitions and performance requirements for Type-C cables, and electromechanical definitions and performance requirements for Type-C cables. C connectors, electromechanical definitions and performance requirements for Type-C connectors, Requirements for Type-C for legacy cable assemblies and adapters, Requirements for Type-C based device detection and interface configuration, Optimized power requirements for Type-C connectors, etc According to USB Type-C specifications, a Type-C port provides VBUS, D+, D, GND, SSTX+, SSTX, SSRX+, and SSRX lines, among others. In addition, a Type-C port also provides a sideband utility line (also known as an SBU) for signaling sideband functionality and a configuration channel (or communication channel, also known as CC) line for detecting, configuring, and managing connections over a Type-C Cable . A Type-C port can be connected to a Type-C plug and/or a Type-C receptacle. For ease of use, the Type-C plug and Type-C receptacle are designed as a reversible pair that works regardless of plug-to-jack orientation. Thus, a standard USB Type-C connector designed as a standard Type-C male or female connector provides pins for four VBUS lines, four ground lines (GND), and two D+ (DP) lines1in PD2), two D lines (DN1a DN2), two SSTX+ lines (SSTXP1an SSTXP2), two SSTX lines (SSTXN1a SSTXN2), two SSRX+ lines (SSRXP1and SSRXP2), two SSRX lines (SSRXN1and SSRXN2), two CC lines (CC1a CC2) and two SBU lines (SBU1an SBU2), among other things.
Some USB-compatible electronic devices may conform to a specific revision and/or version of the USB PD specification. The USB PD specification defines a standard protocol that enables maximum functionality of USB-compatible devices by enabling more flexible power delivery along with data communication over a single USB Type-C cable through USB Type-C ports. The USB PD specification also describes the architecture, protocols, power delivery behavior, parameters, and cabling required to manage power delivery over USB Type-C cables at power levels up to 100W. According to the USB PD specification, devices with USB Type-C connectors (e.g. USB-compatible devices) can handle more power and/or higher or lower voltages over a USB Type-C cable than older USB device specifications (e.g. USB PD). USB 2.0 Specification, the USB 3.1 Specification, the USB Battery Charging Specification Rev. 1.1/1.2, etc.). For example, the USB PD specification defines the requirements for a power supply contract (PD) that can be negotiated between a pair of USB devices. The PD contract can specify both the power level and direction of power transfer that can be supported by both devices, and can be dynamically renegotiated and/or in response to a device's request (e.g. without unplugging the device from the power outlet). various events and conditions, such as B. power roll change, data roll change, hard reset, power source failure, etc. As used herein, "USB PD Subsystem" refers to one or more logic blocks and other analog/digital hardware circuits implemented by firmware in an IC controller and is configured and can be used to perform the functions and meet the requirements specified in at least one version of the USB PD specification. The IC controller can be implemented in a USB Type-C device. The IC controller can be implemented in a USB device.
Power delivery according to the USB PD specification(s) can be realized in various types of USB Type-C applications. Examples of such Type-C applications include, but are not limited to: a Downstream Facing Port (DFP) application, where an IC controller with a USB PD subsystem is configured to provide a downstream USB port ( e.g. host device); an upstream facing port (UFP) application where an IC controller with a USB PD subsystem is configured to provide an upstream facing USB port (e.g., in a USB-enabled peripheral or adapter); a USB dual-roll port (DRP) application, where an IC controller with a USB PD subsystem is configured to support both DFP and UFP applications on the same USB port (e.g., a USB Type-C port that is configured to work as). either a power supplier or a power consumer, or can dynamically switch between these two roles using USB-PD power role swapping); and an active cable application where an IC controller with a USB PD subsystem is packaged and configured for use in a Type-C cable with Electronically Marked Cable Assembly (EMCA).
Details of a buck-boost converter are described below with reference to FIG
Further described herein are various embodiments directed to an IC controller, comprising a controller coupled to a slope compensation circuit, the controller causing the slope compensation circuit to apply a first slope compensation to the input current in a first mode in which the buck The boost converter operates in discontinuous conduction mode (DCM). The controller detects a transition of the buck-boost converter from a first mode with a first duty cycle to a second mode and causes the edge compensation circuit to apply a second edge compensation to the input current. The second slope compensation starts at a maximum offset of the first slope compensation. Details of these embodiments are described below with respect to FIG
In addition, various embodiments are described herein directed to an IC controller that includes a digital control offset mode, as described below with respect to FIG.
In werking buck-boost-converter100Used to provide power with a wide output voltage range (e.g. 3.3V-22V) and a wide load current range (e.g. 0A-5A) for USB PD applications. When there is a big change in Vin112of vout114, buck-boost-converter100goes through different modes like buck mode116, BB-Buck-Modus118, BB-Boost-modus120, of boost-modus122. In addition to the operating voltage, the load current adds two or three additional modes to the buck-boost converter100, including a continuous conduction mode (CCM), a discontinuous conduction mode (DCM), and optionally a jump mode, as described below with respect to FIG.
Aspects of the present disclosure overcome the above deficiencies and may maintain Vout114within +/- 5% for these mode transitions, especially for low Vout voltages, by controlling a slope compensation circuit to eliminate errors caused by a transition, as described in detail below
In at least one embodiment, mode detect logic216receives and measures Vout114a Wine112and determines whether Vin reaches or exceeds a first threshold associated with Vin approaching Vout, for example during a mode transition from BB boost mode to BB buck mode. In at least one embodiment, mode detect logic216determines whether Vout reaches or exceeds a second threshold associated with Vout approaching Vin, for example during a mode transition from BB buck mode to BB boost mode. Alternate mode detection logic216can determine whether buck-boost converter100is in boost mode or buck mode based on Vout and Vin.
As described herein, a USB-C/PD power supply can be used to provide power with a wide output voltage range of 3.3 V to 21.5 V and an input voltage range of 5.0 V to 24 V, and the USB PD power supply Spec requires that the USB-C/PD power supply achieves an output voltage (Vout) within +/-5% during the conduction transition (Vin) and maintains the Vout monotony as it transitions from one voltage to another. Whenever there is a big change in Vin or Vout, a current converter goes through different modes such as buck mode, BB buck mode, BB boost mode or boost mode, and the duty cycle (Ton/Tsw) must be changed immediately during these mode transitions, otherwise there would be severe under/overshoot of Vout and the requirements of the USB PD specification would not be met. For example, if you change the mode from BB-Boost to BB-Buck, the duty cycle should be changed from 15% to 85% as shown in
Ramp compensation can be used as described herein to ensure power converter stability, but the addition of ramp compensation can result in even more movement of the EA output from minimum to maximum duty cycle, which in turn results in Vout undershoot/overshoot , as shown in
The embodiments of the USB controller described here200for a power converter include a mode transition architecture to prevent large EA movements during mode transitions to meet requirements of 5% Vout and monotonicity over a wide input and output range. I refer back to
As described above, USB controller200can be used in CCM or DCM as shown in
In at least one embodiment is logic606detects a transition of a buck-boost converter from a first mode with a first duty cycle to a second mode with a second duty cycle that is less than or greater than the first duty cycle. Capacitor for slope compensation602stores a tilt compensation component during a first cycle. logic606, using the first control signal601can keep or remove the tilt compensation component of a CSA output605to fix an error caused by the transition. The transition between modes can be a mode transition in either direction between BB buck and BB boost modes. In one embodiment, logic606can detect a transition from a buck boost mode following a buck mode (referred to herein as BB buck mode) to a BB boost mode. A charge is stored in the slope compensation capacitor602during a first BB cycle and the load is applied to the CSA output605during a second BB cycle. The application of the charge in the second BB cycle starts the second BB cycle at a higher voltage than the first BB cycle, as shown in FIG.
In at least one embodiment, a slope compensation circuit604, including slope compensation capacitor602and first change608, is controlled by a USB Type-C controller600. In at least one embodiment, a slope compensation circuit604contains further components, e.g. a compensation logic612indicate a digital value607indicates a current609(slope compensation component) generated by a true digital-to-analog converter (DAC).614. The current609, when slope compensation is enabled, is added to a CSA signal611generate CSS605. CSA signal611is an indication of an inductor current from a buck-boost converter and a CSA output605specifies the unslope-compensated coil current or the slope-compensated coil current. The slope compensated inductor current can also be called the offset output of the slope compensation circuit604This will negate any error in the output of the CSA caused by the transition between modes.
In one version a USB Type-C controller600contains a hardware state machine for detecting a transition from a first mode to a second mode and can send one or more control signals to the slope compensation circuit604to eliminate the error in the output caused by the transition.
In one embodiment, a slope compensation circuit700is configured to maintain an output voltage (Vout) within a specified percentage range during a change in an input voltage (Vin) from a first voltage to a second voltage. In another embodiment, a slope compensation circuit700is configured to maintain the monotonicity of Vout during a change in Vout from a first voltage to a second voltage. In one embodiment, a slope compensation circuit700is controlled by a hardware state machine that detects a transition from a first mode to a second mode and sends one or more control signals to the slope compensation circuit700to eliminate the error in the output caused by the transition. Corresponding waveforms are shown below and described with reference to FIG
I refer back to
In another embodiment where the first mode is a BB buck mode, the processing logic causes a charge to be stored on a capacitor during a first BB cycle. The processing logic causes the charge to be applied during a second BB cycle to start the second BB cycle at a higher voltage than the first BB cycle.
In another embodiment where the first mode is a BB gain mode, the processing logic disables slope compensation during a first BB cycle and enables slope compensation during a second BB cycle following the first BB cycle. In one embodiment, the processing logic causes a capacitor to store slope compensation during the first BB cycle, but removes the slope compensation so that it is not applied during the second BB cycle.
In one embodiment, processing logic can detect a transition by measuring an output voltage (Vout) and an input voltage (Vin). The processing logic may determine that the transition from a BB gain mode to a BB buck mode occurs when the input voltage (Vin) reaches or exceeds a first threshold associated with Vin approaching Vout. In another embodiment, the processing logic may determine that the transition from a BB buck mode to a BB boost mode occurs when the output voltage (Vout) reaches or exceeds a second threshold associated with Vout. Vin approaches.
The following embodiments relate to an IC controller that includes a controller coupled to an edge compensation circuit, the controller causing the edge compensation circuit to apply a first edge compensation to the input current in a first mode in which the buck boost converter operates to are used in a DCM. The controller detects a transition of the buck-boost converter from a first mode with a first duty cycle to a second mode and causes the edge compensation circuit to apply a second edge compensation to the input current. The second slope compensation starts at a maximum offset of the first slope compensation. Using the slope compensation component, the same EA voltage can be maintained by adding an offset to the CSA output using slope compensation using a programmable slope percentage per mode, a programmable delayed start of slope compensation , or both. This reduces the amount of movement EA needs with each mode transition. To reduce EA movement, the tilt compensation component is dynamically changed in each mode to reduce EA movement. For example, the tilt compensation component can be turned on after a delay (Td) after a reset (PWM reset). The slope compensation component moves with the PWM, helping to maintain the same EA output voltage. By delaying the tilt compensation component, the offset is added based on the amount of time the switch is on. In addition, the tilt compensation component to be added and the delay for which tilt compensation is turned off are programmable and can be used to further minimize EA's motion. Details of these embodiments are described below with respect to FIG
In other embodiments, the tilt compensation component can be started from a previous cycle to continue adding the same tilt compensation offset to prevent EA movement, as illustrated in FIG.
Adding the same tilt compensation offset can improve low current operation in the DCM. That is, adding the same slope compensation offset to each cycle can improve the Vout ripple, as shown in two separate waveform diagrams
As described above, a mode-based tilt compensation percentage is programmable, as shown in FIG
In addition, the tilt compensation can be programmed to have a different start delay for each mode. Fixed or variable slope compensation percentages allow slope compensation to be added after a programmable delay in the previous cycle. This can help provide a combination of schedules for each mode. For example, a fixed (1×) slope compensation can be activated from the start of a shift cycle. This is perhaps best suited to a buck mode and can offer the benefit of much longer response time and lower ripple. The other modes can be programmed with different delays, slope compensation percentages, or both. An example of a programmable delay mode is shown in FIG
In an alternate variation of the same scheme, called the delayed boost scheme, there are three modes: buck mode, buck-boost mode, and boost mode. The duty cycle transitions smoothly from buck mode to buck-boost mode, eliminating the need for abrupt EA movements. The duty cycle from buck-boost mode to boost mode must be changed from 85% to 15%, which can cause the EA to abruptly change to boost mode. In boost mode, a boost charge cycle is delayed by 70% from the start of the shift cycle when the mode transitions from buck-boost mode to boost mode. Therefore, the slope compensation current is integrated to a value of 85%, which is similar to the buck-boost mode. This boost start delay further decreases as the Vin/Vout ratio decreases, so that the required boost duty cycle is achieved when the deep boost converter enters a deep boost mode.
I refer back to
In another embodiment, the processing logic detects a transition from a BB buck mode to a BB boost mode. In this embodiment, the first slope compensation includes a first slope percentage and the second slope compensation comprises a second slope percentage that differs from the first slope percentage.
In another embodiment, the processing logic in a third mode applies a third slope compensation to the input current. The third tilt compensation includes a third tilt percentage that is different from the first tilt percentage and the second tilt percentage. The third mode can be a buck mode or a boost mode or a BB buck mode or a BB boost mode.
In another embodiment, the processing logic delays a first delay amount (or delay time) before applying the first slope compensation and delays a second delay amount (or delay time) before applying the second slope compensation, the first delay amount, and the second delay amounts. are different. The amount of delay can be a period of time, a specific time interval, a time value of a timer, or the like. In another embodiment, the first tilt compensation and the second tilt compensation each contain a fixed tilt percentage. In another embodiment, the first tilt compensation and the second tilt compensation comprise a variable tilt percentage.
In another embodiment, the processing logic slows down from the start of a shift cycle before applying the second ramp compensation by a delay amount, where the delay amount is a specified percentage of the shift cycle.
The following embodiments are directed to an IC controller that includes a digital control offset mode as described below with respect to FIG
In a conventional scheme for DCM, at the beginning of each clock cycle, the switch is turned on and the inductor current (iL) builds up. This stream is detected by CSA and CSA produces an output called the CSA output. Tilt compensation is the part to be added for current mode instability. CSA components and slope compensation components are added each cycle as CSA output and compared to EA output. When the CSA output reaches the EA level, a control signal (PWM) switches, resetting the switch and causing the inductor current to decrease and reach zero in the DCM. In every DCM cycle, there is a dead time where the inductor current is zero. In the next clock cycle, the switch turns back on and this process repeats. With the conventional scheme, at any mode transition from CCM-DCM or DCM-Skip, the required motion in EA is very high and results in the output falling or exceeding in Vout, which does not meet the USB-PD specification requirements. Due to the tilt compensation component, EA can be a very slow moving signal. For an inductor rating, the output voltage EA is an indication of the power required by the inverter. The higher the voltage, the higher the output power, as the on-time increases with increasing EA power. By using the slope compensation component in the trip time, the same EA voltage can be maintained since using the slope compensation adds an offset to the CSA output. This can reduce the motion required by EA when there is a mode transition between CCM and DCM.
To reduce EA movement, a scheme can be used where the tilt compensation component is dynamically changed each cycle to reduce EA movement. Instead of leaving the slope compensation inactive after the PWM reset, the slope compensation can be enabled after a delay (Td) after the PWM reset. The slope compensation component moves with the PWM, helping to maintain the same EA output voltage. As shown in
In the embodiments described below, different architectures are described to avoid the need for large EA moves during load-based mode transition, i.e. H. from CCM to DCM, which can then meet +/-5% Vout and monotonicity requirements over a wide range to input and output ranges. The skip mode architecture can be implemented to ensure that the buck-boost converter enters and exits skip mode based on output power demand and that no movement is required at the EA level.
Each buck-boost converter must turn the switches on and off to maintain the duty cycle. Since the switch takes a finite amount of time to turn on and off, there is a minimum duty cycle and maximum duty cycle achievable with the buck-boost converter. When the required duty cycle is less than the minimum possible for a buck-boost converter, it enters hopping mode, in which the buck-boost converter switches at the minimum duty cycle for one cycle and does not switch on subsequent cycles, effectively reduce and thus reduce frequency The duty cycle reaches the minimum achieved by the inverter. When the buck boost converter enters skip mode it can remain in skip mode for tens of milliseconds during which EA can drop to a very low level and with each increase in load current EA takes longer to return to its previous value range, which can cause major undershoot problems at the output. In addition, the minimum value of EA varies depending on the mode required for skip mode, making it much more difficult to correctly define skip mode. It can be difficult to accurately determine the skip mode reference1601for the skip mode as the tilt compensation offset is added to the CSA signal205is different in different modes. These components must be carefully designed to accurately predict jump references for entering and exiting a jump mode. Offset CSA signal205can vary greatly depending on the mode and it can be difficult to implement skip mode with this approach.
To overcome the shortcomings described above, the module PWM_OUT1611The pulse can be digitally compared to a minimum pulse width by BB control logic210to skip boarding or disembarking. PWM_OUT1611The pulse is generated by comparing the CSA_OUT signal205with comp_out signal1603with comparator206. Als PWM_OUT1611The pulse has a width greater than a minimum jump ON time, after which a controller exits jump mode and passes through PWM_OUT1611Signal a set_buck1607and/or set_boost1609Signal dependent on buck-boost mode. If PWM_OUT1611If the pulse has a width less than a minimum hop ON time, which means that less power must be delivered than the minimum power in DCM mode, the controller switches to hop mode and does not pass PWM_OUT1611Signal a set_buck1607and set_boost1609signals. Skip-ON time can be programmed to support different applications and optimize efficiency in low power mode. A programmable digital hysteresis can be added between the ON time thresholds for the skip input and skip output pulse widths to ensure no chatter occurs. In this embodiment, no analog block is required to implement the skip mode. This can reduce design complexity. Since a clock signal can be very accurate (e.g. +/-2%) and the resolution of the skip mode is determined by a clock period (e.g. 20 ns, 40 ns or similar), the skip mode is also In- and exit can be accurately predicted and controlled.
As shown in
I refer back to
In another embodiment, instead of measuring the pulse width over one cycle to detect the hopping mode, the pulse widths can be averaged over multiple cycles to remove any PWM interference. In another embodiment, the dead time after which ramp compensation begins may be programmable and vary from cycle to cycle. In another embodiment, the slope compensation components added during the switch on and off times may be different and changed to minimize the ripple in Vout. In another embodiment, the dead time and edge compensation components added during the switch's on and off times can be changed in each cycle to achieve a fixed offset, making it independent of small signal noise in the PWM.
In one embodiment, the mode transition architecture can be used for any buck-boost converter in a USB PD application. In another embodiment, the mode transition architecture for each buck-boost converter can be used in other applications. In another embodiment, the mode transition architecture can be used in gain converters. In another embodiment, the mode transition architecture can also be used in other power converters.
The mode transition architecture embodiments described herein can provide a simpler architecture with less design complexity. Control logic implementing the mode transition techniques described herein can be implemented in circuits using Register Transfer Level (RTL). Mode transition architecture implementations can also have a small chip area. Embodiments of mode transition architectures can operate seamlessly between CCM and DCM mode operation. Implementations of mode transition architectures can allow for lower load capacitance, as there is less IO movement and a capacitor is required to support the load current during this time, reducing the amount of capacitance, the bill of material (BOM) cost, and space requirement on a plate be lowered. In some embodiments, firmware can be used to change a scheme in different converter modes. Firmware can provide programmable options to tune each mode based on customer specific operating modes, e.g. B. buck only modes or boost only modes and even older modes of operation. Firmware provides flexibility in using the IC controller in different applications, programmability and fast design time for implementing the IC controller in a new application. Implementations of the digital skip mode architecture can reduce the accuracy requirements of the CSA and tilt compensation blocks. This also reduces design complexity by providing simpler block components, smaller die area and lower power consumption. In addition, the digital skip-mode architecture as described here can be very accurate, as the accuracy depends on the clock frequency (e.g. 24 MHz), which can be easily achieved in terms of performance. A digitally controlled input skip threshold can be programmable to achieve optimum efficiency in a power saving mode for different applications. This can provide scalability and programmability in different applications.
CPU-subsystem2102contains one or more CPUs2104, Flash memory2106, SRAM (static random access memory)2108en ROM (Read Only Memory)2110associated with the system connection2112. CPU2104is a suitable processor that can be used in an IC or a SoC device. Flash memory2106is non-volatile memory (e.g., NAND flash, NOR flash, etc.) configured to store data, programs, and/or other firmware instructions. Flash memory2106is closely related to the CPU subsystem2102for improved access times. SRAM2108is volatile memory configured to store data and firmware instructions that the CPU can access2104. Rom2110is read-only memory (or other suitable storage medium) configured to store boot routines, configuration parameters, and other firmware parameters and settings. system connection2112is a system bus (e.g., a single-tier or multi-tier Advanced High-Performance Bus, or AHB) configured as an interface that links the various components of the CPU subsystem2102each other and as a data and control interface between the various components of the CPU subsystem and the peripheral link2114.
peripheral connection2114is a peripheral bus (for example, a single-level or multi-level AHB) that provides the primary data and control interface between the CPU subsystem2102and its peripherals and other resources, such as B. System resources2116, E/A subsystem2118and USB PD subsystem2120. The peripheral connection2114may include various controller circuits (e.g., direct memory access or DMA controllers) that can be programmed to transfer data between peripheral blocks without burdening the CPU subsystem2102. In various embodiments, each of the components of the CPU subsystem and peripheral connection may vary depending on the choice or type of CPU, system bus, and/or peripheral bus.
system resources2116consist of various electronic circuits that support the operation of the IC controller2100in its various states and modes. For example system resources2116may contain a power subsystem with analog and/or digital circuitry required for each state/mode of the controller, such as sleep control circuitry, wake-up interrupt controller (WIC), power-on-reset (POR), voltage and/or or current reference circuits (REF), etc. In some embodiments, the power subsystem may also contain circuits that allow IC control2100to generate and/or supply power from/to external sources at multiple different voltage and/or current levels and to support controller operation in multiple power states2117(e.g. active state, sleep state and deep sleep state with clocks off). In addition, in some embodiments, the CPU subsystem2102can be optimized for power-efficient operation with extended clock ports and can include several internal controller circuits that allow the CPU to operate in different power states2117. For example, the CPU may include a wake-up interrupt controller configured to wake the CPU from a sleep state, allowing power to be turned off when the IC chip is in a sleep state. system resources2116may also include a clock subsystem having analog and/or digital circuitry for clock generation and clock management, such as clock control circuitry, watchdog timer circuitry (WDT), and internal low-speed oscillator circuitry (ILO). ) and internal main oscillator circuit(s), etc. System resources2116May also include analog and/or digital circuit blocks that provide reset control and support remote reset (XRES).
In various versions, I/O subsystem2118may contain different types of I/O blocks and subsystems. For example in the illustrated version
USB-PD subsystem2120Provides the interface to a USB Type-C connector and is configured to support USB communication and other USB functions such as power delivery and battery charging. USB PD subsystem2120Contains the electrostatic discharge (ESD) protection circuitry required for a Type-C connector. USB PD subsystem2120Also includes a Type-C transceiver and physical layer logic (PHY) configured as a baseband PHY integrated circuit to perform various digital encoding/decoding functions (e.g. Biphase Mark Code-BMC encoding/decoding, cyclic redundancy checks-CRC, etc. ) and analog signal processing functions involved in physical layer transmissions. USB PD subsystem2120also provides the terminating resistors (RP and RD) and their switches as required by the USB PD specification to implement connection sensing, connector orientation sensing, and power delivery functions over a Type-C cable. IC controller2100(and/or the USB PD subsystem2120thereof) can also be configured to respond to communications defined in a USB PD specification, such as Start-of-Packet (SOP), SOP′, and SOP″ messages.
Including the USB PD subsystem2120may also include: one or more analog-to-digital converters (ADCs) for converting various analog signals to digital signals; a VCONN FET; an error amplifier (ERROR AMP) for controlling the current source voltage applied to the VBUS line according to a PD contract; a high voltage regulator (HV REG) to convert the supply voltage to the exact voltage (e.g. 3-5V) required by the IC controller2100; a current sense amplifier (CSA) and overvoltage protection circuit (OVP) to provide overcurrent (OCP), overvoltage (OV), and undervoltage (UV) protection on the VBUS line with configurable thresholds and response times; a pulse width modulator (PWM); one or more gate drivers (GATE DRV) to control the power switches that turn the power on and off over the VBUS line; a low-side gate driver (LSDR), a high-side gate driver (HSDR) for controlling switches of the buck-boost converter; communication channel PHY logic (CC BB PHY) to support communication on a Type-C communication channel line (CC); a load protocol detection block (CHG DET) to detect different types of PD loaders; and at least two on-chip discharge circuits (VBUS DISCH) capable of discharging a VBUS line voltage to any programmable voltage level.
Different implementations of the USB-C mode transition architecture described herein may involve different operations. These operations can be performed and/or controlled by hardware components, digital hardware and/or firmware and/or combinations thereof. As used herein, the term "linked to" can mean linked directly or indirectly through one or more intermediate components. Each of the signals delivered over different on-chip buses can be time-multiplexed with other signals and delivered over one or more common on-die buses. In addition, the connection between circuit components or blocks can be represented as buses or as separate signal lines. Each of the buses may alternatively be one or more individual signal lines, and each of the individual signal lines may alternatively be buses.
Certain embodiments may be implemented by firmware instructions stored on a non-temporary computer readable medium, e.g. B. a volatile memory and/or a non-volatile memory. These instructions can be used to program and/or configure one or more devices, including processors (e.g., CPUs) or equivalents thereof (e.g., processing cores, processing engines, microcontrollers, and the like), so that they run when executed by the processor(s). ) or their equivalent, the instructions cause the device(s) to perform the operations described for the USB-C mode transition architecture described herein. The non-temporary computer readable storage medium may include, but is not limited to, an electromagnetic storage medium, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or a other now known or later developed non-volatile medium suitable for storing information.
Although the operations of the circuit(s) and blocks are shown and described herein in a particular order, in some embodiments the order of the operations of each circuit/block may be rearranged so that certain operations can be performed in the reverse order or so that certain operations operations can be performed at least partially simultaneously and/or in parallel with other operations. In other embodiments, instructions or sub-operations of different operations may be executed intermittently and/or alternately.
In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.