U.S. Patent for Mode Transition Architecture for Buck-Boost Converters (Patent No. 11,658,573, issued May 23, 2023) (2023)

PRIORITY

This application claims the benefits of U.S. Provisional Application No. 63/074,270, filed September 3, 2020, and U.S. Provisional Application No. 63/074,296, filed September 3, 2020. The entire contents of both applications are incorporated by reference incorporated herein in their entirety.

TECHNICAL FIELD

This disclosure pertains to integrated circuits (ICs) that control power to electronic devices over the Universal Serial Bus (USB).

BACKGROUND

Various electronic devices (e.g. smartphones, tablets, notebooks, laptops, chargers, adapters, power banks, etc.) are configured to transfer power through USB ports according to USB power delivery protocols, which are available in different versions and revisions defined by the USB Power Delivery (USB-PD) specification. For example, in some applications, an electronic device can be configured as a power consumer that receives power from a USB port (for example, to charge the battery), while in other applications, an electronic device can be configured as a power source to provide power. another device Power device connected to it through a USB port. In various applications, electronics manufacturers may also use power converters (e.g., buck-boost converters) that must meet various USB PD specification requirements, such as output voltage (Vout), monotonicity, and stability requirements.

DETAILED DESCRIPTION

The following description contains numerous specific details such as examples of specific systems, components, methods, etc. to provide a thorough understanding of various implementations of the USB Type-C controller mode transition architecture described herein. However, it will be apparent to those skilled in the art that at least some embodiments can be practiced without these specific details. In other cases, known components, elements, or methods are not described in detail or are presented in a simple block diagram to avoid unnecessarily obscuring the topic being described. Therefore, the specific details set forth below are examples only. Certain implementations may differ from these exemplary details and still be considered within the spirit and scope of the present embodiments.

References in the specification to "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," and "various embodiments" mean that a particular feature, structure, step, operation, or specific feature described in connection with that embodiment (s) is included in at least one embodiment. In addition, the terms "an embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", and "various embodiments" in the specification do not necessarily refer to the same embodiment(s). ).

The description includes references to the accompanying drawings, which form part of the detailed description. The drawings show representations according to exemplary embodiments. These embodiments, which may also be referred to herein as "examples", are described in sufficient detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The performances may be combined, other performances may be used, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the subject matter claimed. It is to be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable any person skilled in the art to practice, make and/or use the subject matter.

Describes various embodiments of a mode transition architecture in USB Type-C controllers that can be deployed to operate in various electronic devices. Examples of such electronic devices include, but are not limited to, personal computers (e.g., laptops, notebooks, etc.), mobile computing devices (e.g., tablets, tablet computers, e-readers, etc.), mobile communications devices (e.g., smartphones, mobile phones, personal digital assistants, messaging devices, pocket PCs, etc.), connectivity and charging devices (e.g. cables, hubs, docking stations, adapters, chargers, etc.), audio/video/data recording and/or playback devices (e.g. cameras, voice recorders, handheld scanners, monitors, etc.) and other similar electronic devices that may use USB interfaces for communication, battery charging, and/or power.

As used herein, "USB-compatible" device or system refers to a device or system that contains a USB connection interface, is configured with, or is otherwise connected to a USB connection interface. A USB-compatible electronic device can conform to at least one version of a Universal Serial Bus (USB) specification. Examples of such USB specifications include, but are not limited to, the USB Revision 2.0 specification, the USB 3.0 specification, the USB 3.1 specification, the USB 3.2 specification and/or various amendments, versions and errata thereof. The USB specifications generally define the characteristics (e.g., attributes, protocol definition, transaction types, bus management, programming interfaces, etc.) of a differential serial bus necessary for designing and building standard communications systems and peripherals. For example, a USB-compatible peripheral device is connected to a USB-compatible host device through a USB port of the host device to form a USB-compatible system. A USB 2.0 port contains a 5V power line (labeled VBUS), a differential pair of data lines (labeled D+ or DP and D− or DN), and a power return ground line (labeled GND). A USB 3.0 connector also provides the VBUS, D+, D−, and GND lines for backward compatibility with USB 2.0. To support a faster differential bus (the USB SuperSpeed ​​bus), a USB 3.0 port also provides a differential pair of transmitter data lines (labeled SSTX+ and SSTX−) and a differential pair of receiver data lines (labeled SSRX+ and SSRX−), a power line for power (also referred to as DPWR) and a power return ground (also referred to as DGND). A USB 3.1 port provides the same lines as a USB 3.0 port for backward compatibility with USB 2.0 and USB 3.0 communications, but improves SuperSpeed ​​bus performance with a suite of features known as Enhanced SuperSpeed.

A newer USB connector technology called USB Type-C (also referred to herein as "USB-C") is defined in various versions and/or revisions of the USB Type-C specification. The USB Type-C specification defines Type-C connectors, Type-C plugs and Type-C cables that can support both USB communication and power delivery over newer USB power delivery protocols available in different revisions/versions of the USB PD specification are defined. Examples of USB Type-C capabilities and requirements include USB 2.0 and USB 3.0/3.1 data and other communications, electromechanical definitions and performance requirements for Type-C cables, and electromechanical definitions and performance requirements for Type-C cables. C connectors, electromechanical definitions and performance requirements for Type-C connectors, Requirements for Type-C for legacy cable assemblies and adapters, Requirements for Type-C based device detection and interface configuration, Optimized power requirements for Type-C connectors, etc According to USB Type-C specifications, a Type-C port provides VBUS, D+, D, GND, SSTX+, SSTX, SSRX+, and SSRX lines, among others. In addition, a Type-C port also provides a sideband utility line (also known as an SBU) for signaling sideband functionality and a configuration channel (or communication channel, also known as CC) line for detecting, configuring, and managing connections over a Type-C Cable . A Type-C port can be connected to a Type-C plug and/or a Type-C receptacle. For ease of use, the Type-C plug and Type-C receptacle are designed as a reversible pair that works regardless of plug-to-jack orientation. Thus, a standard USB Type-C connector designed as a standard Type-C male or female connector provides pins for four VBUS lines, four ground lines (GND), and two D+ (DP) lines1in PD2), two D lines (DN1a DN2), two SSTX+ lines (SSTXP1an SSTXP2), two SSTX lines (SSTXN1a SSTXN2), two SSRX+ lines (SSRXP1and SSRXP2), two SSRX lines (SSRXN1and SSRXN2), two CC lines (CC1a CC2) and two SBU lines (SBU1an SBU2), among other things.

Some USB-compatible electronic devices may conform to a specific revision and/or version of the USB PD specification. The USB PD specification defines a standard protocol that enables maximum functionality of USB-compatible devices by enabling more flexible power delivery along with data communication over a single USB Type-C cable through USB Type-C ports. The USB PD specification also describes the architecture, protocols, power delivery behavior, parameters, and cabling required to manage power delivery over USB Type-C cables at power levels up to 100W. According to the USB PD specification, devices with USB Type-C connectors (e.g. USB-compatible devices) can handle more power and/or higher or lower voltages over a USB Type-C cable than older USB device specifications (e.g. USB PD). USB 2.0 Specification, the USB 3.1 Specification, the USB Battery Charging Specification Rev. 1.1/1.2, etc.). For example, the USB PD specification defines the requirements for a power supply contract (PD) that can be negotiated between a pair of USB devices. The PD contract can specify both the power level and direction of power transfer that can be supported by both devices, and can be dynamically renegotiated and/or in response to a device's request (e.g. without unplugging the device from the power outlet). various events and conditions, such as B. power roll change, data roll change, hard reset, power source failure, etc. As used herein, "USB PD Subsystem" refers to one or more logic blocks and other analog/digital hardware circuits implemented by firmware in an IC controller and is configured and can be used to perform the functions and meet the requirements specified in at least one version of the USB PD specification. The IC controller can be implemented in a USB Type-C device. The IC controller can be implemented in a USB device.

Power delivery according to the USB PD specification(s) can be realized in various types of USB Type-C applications. Examples of such Type-C applications include, but are not limited to: a Downstream Facing Port (DFP) application, where an IC controller with a USB PD subsystem is configured to provide a downstream USB port ( e.g. host device); an upstream facing port (UFP) application where an IC controller with a USB PD subsystem is configured to provide an upstream facing USB port (e.g., in a USB-enabled peripheral or adapter); a USB dual-roll port (DRP) application, where an IC controller with a USB PD subsystem is configured to support both DFP and UFP applications on the same USB port (e.g., a USB Type-C port that is configured to work as). either a power supplier or a power consumer, or can dynamically switch between these two roles using USB-PD power role swapping); and an active cable application where an IC controller with a USB PD subsystem is packaged and configured for use in a Type-C cable with Electronically Marked Cable Assembly (EMCA).

Details of a buck-boost converter are described below with reference to FIGAFB.1A-1F. It also describes several embodiments directed to an IC controller consisting of a controller coupled to a transconductance compensation circuit, the controller switching a buck-boost converter from a first mode with a first duty cycle to a second mode, a second duty cycle detects a cycle that is less than the first duty cycle. The controller controls the slope compensation circuit to eliminate an error in an output caused by the transient. The controller can cause the transconductance compensation circuit to apply a charge stored on a capacitor during a first cycle to start a second cycle at a higher voltage than the first cycle. Details of these embodiments are described below with respect to FIGAFB.2-10.

Further described herein are various embodiments directed to an IC controller, comprising a controller coupled to a slope compensation circuit, the controller causing the slope compensation circuit to apply a first slope compensation to the input current in a first mode in which the buck The boost converter operates in discontinuous conduction mode (DCM). The controller detects a transition of the buck-boost converter from a first mode with a first duty cycle to a second mode and causes the edge compensation circuit to apply a second edge compensation to the input current. The second slope compensation starts at a maximum offset of the first slope compensation. Details of these embodiments are described below with respect to FIGAFB.11-15.

In addition, various embodiments are described herein directed to an IC controller that includes a digital control offset mode, as described below with respect to FIG.AFB.16-20.

FEIGE.1AFigure 12 is a schematic diagram of a buck-boost converter100in at least one embodiment. buck-boost converter100contains an inducer102, a first switch104, a second switch106, a third switch108and a fourth switch110. Switch104In110are also referred to as high-side switches (HS) and switches106In108are called low-side switches (LS). First change104is linked to an input voltage (Vin).112and fourth switch110is linked to an output voltage (Vout).114. The switches can be operated to operate the buck boost converter100in one of four modes, including a buck mode116, a buck-boost (BB) buck mode118, a BB boost mode120and a boost mode122, as shown in an image130vonAFB.1B-1F.

FEIGE.1Bis a graph13012 illustrates three modes of a buck-boost converter and transitions between the three modes as a function of input voltage (Vin).112and an output voltage (Vout)114in at least one embodiment.FEIGE.1Cis a time map132of control signals from a buck-boost converter in a buck mode in at least one embodiment.FEIGE.1Dis a time map134of control signals from a buck-boost converter in a buck-boost mode after a buck-mode (BB-Buck) in at least one embodiment.FEIGE.1Eis a time map136of control signals from a buck-boost converter in a buck-boost mode following a boost (BB-boost) mode in at least one embodiment.FEIGE.1Fis a time map138of control signals from a buck-boost converter in a boost mode in at least one embodiment.

In werking buck-boost-converter100Used to provide power with a wide output voltage range (e.g. 3.3V-22V) and a wide load current range (e.g. 0A-5A) for USB PD applications. When there is a big change in Vin112of vout114, buck-boost-converter100goes through different modes like buck mode116, BB-Buck-Modus118, BB-Boost-modus120, of boost-modus122. In addition to the operating voltage, the load current adds two or three additional modes to the buck-boost converter100, including a continuous conduction mode (CCM), a discontinuous conduction mode (DCM), and optionally a jump mode, as described below with respect to FIG.AFB.16-21. buck-boost converter100operates in CCM mode at higher load current with fixed switching frequency. buck-boost converter100operates in DCM mode at moderate load current with fixed switching frequency. buck-boost converter100can be operated in a hopping mode (lower frequency) at low load current for best efficiency, as described here. The duty cycle (Ton/Tsw) must be changed immediately during these mode transitions, otherwise severe under/overshoot of Vout would occur114and may not meet a requirement of the USB PD specification. For example, a mode transition from BB-Boost to BB-Buck requires a duty cycle change from 15% to 85%. To ensure the stability of the inverter, slope compensation is required. Adding slope compensation may result in even more movement of the error amplifier output (EA) from minimum duty cycle to maximum duty cycle, which in turn may result in Vout114fall below or exceed. With limited gain and loop bandwidth, the loop itself cannot support Vout114within +/-5% for these mode transitions, especially at low Vout voltages.

Aspects of the present disclosure overcome the above deficiencies and may maintain Vout114within +/- 5% for these mode transitions, especially for low Vout voltages, by controlling a slope compensation circuit to eliminate errors caused by a transition, as described in detail belowAFB.2-10. Aspects of the present disclosure overcome the above deficiencies and may maintain Vout114within +/- 5% for these mode transitions, especially for low Vout voltages, by controlling a slope compensation circuit to start slope compensation from a previous cycle and continue adding an equal slope compensation offset to compensate for motion of an EA output as described in detail belowAFB.11-15.

FEIGE.2Figure 12 is a block diagram of a USB controller200linked to a buck-boost converter100in at least one embodiment. USB controller200contains a current sense amplifier (CSA)202, a slope compensation circuit204, a comparator206, an error amplifier (EA)208, BB control logic210, manager212, manager214and mode detection logic216. CSA202Can measure an input current of a buck-boost converter100and can issue a CSA signal201Displays the input current. tilt compensation circuit204, which may contain slope compensation logic and a slope compensation capacitor as described herein, is coupled to an output of CSA202. tilt compensation circuit204can add an offset signal203(slope compensation offset) on the CSA signal201when activated, an offset CSA signal is generated205. In some cases the offset signal203is a current or charge. In other cases the offset signal203can be a voltage signal if other circuits are used to add the offset signal203on the CSA signal201. comparator206receives the offset CSA signal205and an EA signal207by EA208. EA208compares Vout114against a voltage reference to generate an IO signal207. comparator206compares the offset CSA signal205and EA signal207and outputs a control signal209, also called pulse width modulation (PWM), is passed to the BB control logic210. BB control logic210receives control signal209and one mode signal211by the mode detection logic216. Mode detection logic216can determine a mode and a transition between modes based on Vout114a Wine112and outputs a mode signal211corresponding. BB control logic210uses the control signal209and mode signal211to control a mode of a buck-boost converter100. Specifically, the BB control logic210can send a first control signal213to the driver212which controls the first and second switches of the buck-boost converter100and a second control signal215to the driver214which controls the third and fourth switches of the step-down converter100.

In at least one embodiment, mode detect logic216receives and measures Vout114a Wine112and determines whether Vin reaches or exceeds a first threshold associated with Vin approaching Vout, for example during a mode transition from BB boost mode to BB buck mode. In at least one embodiment, mode detect logic216determines whether Vout reaches or exceeds a second threshold associated with Vout approaching Vin, for example during a mode transition from BB buck mode to BB boost mode. Alternate mode detection logic216can determine whether buck-boost converter100is in boost mode or buck mode based on Vout and Vin.

As described herein, a USB-C/PD power supply can be used to provide power with a wide output voltage range of 3.3 V to 21.5 V and an input voltage range of 5.0 V to 24 V, and the USB PD power supply Spec requires that the USB-C/PD power supply achieves an output voltage (Vout) within +/-5% during the conduction transition (Vin) and maintains the Vout monotony as it transitions from one voltage to another. Whenever there is a big change in Vin or Vout, a current converter goes through different modes such as buck mode, BB buck mode, BB boost mode or boost mode, and the duty cycle (Ton/Tsw) must be changed immediately during these mode transitions, otherwise there would be severe under/overshoot of Vout and the requirements of the USB PD specification would not be met. For example, if you change the mode from BB-Boost to BB-Buck, the duty cycle should be changed from 15% to 85% as shown inFEIGE.3.

FEIGE.3is a time map300een buck duty-cycle302and a boost duty cycle304as a function of an input voltage (Vin) in at least one embodiment. In boost mode306, Buck-werkcyclus302has a duty cycle of 1.0. In a buck-boost mode308, Buck-werkcyclus302has a duty cycle of 0.85 for part of the buck-boost mode308and transitions to a duty cycle of 0.7 through another part of the buck-boost mode308. I am Buck Mode310, Buck-werkcyclus302Transitions between about 0.79 and 0.55. In boost mode306, increase the duty cycle304Transitions between about 0.69 and 0.2. In a buck-boost mode308, increase the duty cycle304has a duty cycle of 0.15 for part of the buck-boost mode308and transitions from 0.15 to about 0.3 through another part of the buck-boost mode308. I am Buck Mode310, increase the duty cycle304has a duty cycle of 0.

Ramp compensation can be used as described herein to ensure power converter stability, but the addition of ramp compensation can result in even more movement of the EA output from minimum to maximum duty cycle, which in turn results in Vout undershoot/overshoot , as shown inAFB.4A-4B.FEIGE.4Ais a time map400a CSA signal402with slope compensation added to an input current to a buck-boost converter in at least one embodiment.FEIGE.4Bis a time map420Illustration of a breached condition422to an output voltage (Vout) caused by edge compensation during a transition from a BB boost mode to a BB buck mode in at least one embodiment. In some cases with limited gain and loop bandwidth of a loop with the EA, the loop itself cannot keep Vout within +/-5% for these mode transitions, especially at low Vout voltages.

The embodiments of the USB controller described here200for a power converter include a mode transition architecture to prevent large EA movements during mode transitions to meet requirements of 5% Vout and monotonicity over a wide input and output range. I refer back toFEIGE.2, USB-controller200may include a controller consisting of, for example, slope compensation logic or slope compensation circuits204, Mode detection logic216controlling the ramp compensation circuit to eliminate an error caused by a transition from a first mode with a first duty cycle to a second mode with a second duty cycle. The second duty cycle can be shorter than the first duty cycle. Alternatively, the second duty cycle may be greater than the first duty cycle, depending on the mode convention. The controller can detect a buck-boost converter transition100from a first mode (e.g., BB buck mode) with a first duty cycle (e.g., 85%) to a second mode (e.g., BB boost mode) with a second duty cycle (e.g., 15%) that is less than the first duty cycle. The controller can control the slope compensation circuit204to cancel an error in the output caused by the transition. The controller can detect a buck-boost converter transition100from the second mode to the first mode and can control the slope compensation circuit204to eliminate an error in the output caused by the transition (e.g. 15% to 85% duty cycle).

As described above, USB controller200can be used in CCM or DCM as shown inFEIGE.5A.

FEIGE.5Ais a time map500an inductor current and a control signal in a continuous conduction mode (CCM) and in a discontinuous conduction mode (DCM) in at least one embodiment. USB controller200is in CCM when the inductor current502does not go to zero every cycle, which always energizes the inductor. CCM is used to support higher load current. The operating frequency is constant in this mode. USB controller200is in DCM when the inductor current504goes to zero in each cycle, leaving the inductor de-energized for a certain amount of time during the cycle. This period is called dead time. DCM is used to support moderate load current. The operating frequency is constant in this mode. timetable500also shows a control signal506(e.g. PWM output) sent to the BB control logic to control the operation of the buck-boost converter in the CCM and provide a control signal508(e.g. PWM output) sent to the BB control logic to control the operation of the buck boost converter in the DCM. The different signals, including slope compensation, during DCM are described below as an example.

FEIGE.5Bis a time map550Illustrating a current output signal (CSA out) based on an input current component (CSA) and a slope compensation component in at least one embodiment. At the beginning of each clock cycle, a buck-boost converter switch is turned on and an inductor current (iL) is generated.552builds up. The coil current552is captured by a CSA and produces an output called CSA component554. The slope compensation circuit generates a slope compensation component556This was added for current mode instability. CSA component554and tilt compensation component556are added as CSA-out558and compared to the output level of the error amplifier (EA).560every cycle. For an inductor rating, the EA output voltage is an indication of the power required by the buck-boost converter. The higher the voltage, the higher the output power, because the on-time increases as the IO output increases. Down with the CSA558reaches EA level560, a control signal562(PWM) toggles and resets the switch, decreasing the inductor current until it reaches zero in the DCM. In every DCM cycle, there is a dead time where the inductor current is zero. In the next clock cycle, the switch turns back on and this process repeats. For some mode transitions, the required motion in EA can be very high and cause the output to go too low or too high. The under or over conditions can cause the output voltage to vary by an amount greater than a USB PD specification allows. EA is a very slow signal due to the connected compensation component. By using the slope compensation component through a slope compensation circuit as shown in FIGAFB.6-7, the same EA voltage can be maintained, reducing the required movement of EA at each mode transition, as shown in FIG.FEIGE.8. As described herein, in addition to controlling the slope compensation circuitry to cancel an error, the slope percentage and delay for starting slope compensation are also programmable, further minimizing EA's motion.

FEIGE.6Figure 1 is a block diagram of a USB Type-C controller600which controls a transconductance compensation capacitor602a slope compensation circuit604to clear an error caused by a transition in at least one embodiment. USB Type-C controller600includes logic606capable of detecting a transition of a buck-boost converter from a first mode to a second mode, as described herein. logic606outputs a first control signal601(cap_reset) to reset the slope compensation capacitor602using a first switch608and outputs a second control signal603(csa_reset) to reset a CSA output with a second switch610.

In at least one embodiment is logic606detects a transition of a buck-boost converter from a first mode with a first duty cycle to a second mode with a second duty cycle that is less than or greater than the first duty cycle. Capacitor for slope compensation602stores a tilt compensation component during a first cycle. logic606, using the first control signal601can keep or remove the tilt compensation component of a CSA output605to fix an error caused by the transition. The transition between modes can be a mode transition in either direction between BB buck and BB boost modes. In one embodiment, logic606can detect a transition from a buck boost mode following a buck mode (referred to herein as BB buck mode) to a BB boost mode. A charge is stored in the slope compensation capacitor602during a first BB cycle and the load is applied to the CSA output605during a second BB cycle. The application of the charge in the second BB cycle starts the second BB cycle at a higher voltage than the first BB cycle, as shown in FIG.FEIGE.8. In another embodiment, logic606can detect a transition from a BB boost mode to a BB buck mode. A charge can be stored by a capacitor for transconductance compensation602, Logic606disables tilt compensation for a full first BB boost cycle. For example logic606can send the first control signal601to discharge the slope compensation capacitor602thus no tilt compensation component is added to the CSA output605. In some cases, charge is stored during a first cycle and removed during a second cycle.

In at least one embodiment, a slope compensation circuit604, including slope compensation capacitor602and first change608, is controlled by a USB Type-C controller600. In at least one embodiment, a slope compensation circuit604contains further components, e.g. a compensation logic612indicate a digital value607indicates a current609(slope compensation component) generated by a true digital-to-analog converter (DAC).614. The current609, when slope compensation is enabled, is added to a CSA signal611generate CSS605. CSA signal611is an indication of an inductor current from a buck-boost converter and a CSA output605specifies the unslope-compensated coil current or the slope-compensated coil current. The slope compensated inductor current can also be called the offset output of the slope compensation circuit604This will negate any error in the output of the CSA caused by the transition between modes.

InFEIGE.6, USB-Type-C-controller600controls the slope compensation circuit604to keep or remove a tilt compensation component from the previous mode and move to the next mode. The slope compensation component introduces the error (or offset) when going from, say, the 85% duty cycle of BB buck mode to the 15% duty cycle of BB boost mode. This error is canceled by the slope compensation holding capacitor602in a BB buck cycle by not resetting the transconductance compensation capacitor and starting the CSA output605with a higher voltage in a subsequent cycle. This causes the duty cycle to transition from 85% duty cycle in BB buck mode to 15% duty cycle in BB boost mode without moving EA. Similarly, a mode transition from BB Boost mode to BB Buck mode removes the tilt compensation component by holding down the first switch608for a certain time, e.g. B. Enabled a full cycle. In one version a USB Type-C controller600is configured to maintain an output voltage (Vout) within a specified percentage range during a change in an input voltage (Vin) from a first voltage to a second voltage. In another version, a USB Type-C controller600is configured to maintain the monotonicity of Vout during a change in Vout from a first voltage to a second voltage.

In one version a USB Type-C controller600contains a hardware state machine for detecting a transition from a first mode to a second mode and can send one or more control signals to the slope compensation circuit604to eliminate the error in the output caused by the transition.

FEIGE.7Figure 12 is a schematic diagram of a slope compensation circuit700which is controlled to clear an error caused by a transition in at least one embodiment. tilt compensation circuit700receives an input stream701of a KSA702and converts the input current into an input voltage703. Ein Unity-Gain-Puffer704input voltage can be received703to generate a CSA signal705. tilt compensation circuit700Also includes a capacitor706and a programmable power source708generating a tilt compensation signal707. condenser706is linked to an output node and the output of CSA702. condenser706stores a compensation that can be applied as an initial compensation in the CSA output709during a subsequent cycle. That is, a slope compensation circuit700can save a slope compensation component from a previous mode to move to a next mode. Programmable power source708can be activated or deactivated via a switch712with a control signal713(scomp_nl). As described above, the slope compensation component introduces the error (or offset) during the transition from a first duty cycle to a second duty cycle that is shorter than the first duty cycle. The error is cleared by holding the charge in the capacitor706by not resetting a switch710with a control signal711(scap_rst) and start CSA output709with a higher voltage in a subsequent cycle. switch710is coupled between the exit node and the exit of the CSA702. This causes the first duty cycle (e.g. 85% in BB buck mode) to transition to the second duty cycle (e.g. 15% in BB boost mode) without moving EA. Similarly, in a mode transition from the second mode to the first mode, the transconductance compensation component is removed from the capacitor706by resetting the switch710for a certain amount of time, e.g. a whole cycle. Compensation logic in a controller, or a state machine in the controller, can be configured to track these transitions and initiate control signals711,713corresponding. Also a switch714can be controlled by a control signal (RST_SW) that resets the CSA signal705.

In one embodiment, a slope compensation circuit700is configured to maintain an output voltage (Vout) within a specified percentage range during a change in an input voltage (Vin) from a first voltage to a second voltage. In another embodiment, a slope compensation circuit700is configured to maintain the monotonicity of Vout during a change in Vout from a first voltage to a second voltage. In one embodiment, a slope compensation circuit700is controlled by a hardware state machine that detects a transition from a first mode to a second mode and sends one or more control signals to the slope compensation circuit700to eliminate the error in the output caused by the transition. Corresponding waveforms are shown below and described with reference to FIGAFB.8-9B.

FEIGE.8is a time map800Representation of a current output signal (CSA out) based on an input current component (CSA) and a slope compensation component, where a charge stored during a previous cycle is applied to start a next cycle in at least one cycle with a higher voltage than the previous one cycle. timetable800illustrates a transition from a BB buck mode802in a BB boost mode804. Timetable800illustrates a CSA signal806with a slope compensation that is added to an input current and indicates the inductor current (IL). During a first BB cycle in BB buck mode802, a first slope compensation808is applied. During a second BB Boost cycle in BB Boost mode804, a second slope compensation810is applied. As described above, a capacitor can store a charge during the first BB cycle and by applying the charge in the second BB cycle it can start the second BB cycle with a higher voltage812as starting voltage814of the first BB cycle.

FEIGE.9Ais a time map900an input voltage (Vin)902and an output voltage (Vout)904Using a slope compensation circuit to cancel an error caused by a transition in at least one embodiment. As shown inFEIGE.9A, the slope compensation Vout can be maintained904through a mode transition.

FEIGE.9Bis a time map920of control signals to control a slope compensation circuit to cancel an error caused by a transient in at least one embodiment. timetable920a first transition between a BB buck mode and a BB boost mode and a second transition from a BB boost mode to a BB buck mode. timetable920illustrates a CSA signal922with a slope compensation that is added to an input current and indicates the inductor current (IL). For the first transition, a first slope compensation is applied during a first BB cycle in BB buck mode and a second slope compensation during a subsequent cycle in BB boost mode. As described above, a capacitor can store a charge during the first BB cycle and by applying the charge in the second BB cycle, the second BB cycle starts the second BB cycle at a higher voltage928as the starting voltage of the first BB cycle. This can be controlled with the aid of a first control signal924and a second control signal926. First steering signal924The capacitor and the second control signal are not reset926turns off the slope compensation circuit so the voltage is higher928applied during the second BB cycle. For the second transition, a first slope compensation is applied during a third BB cycle in BB boost mode and a second slope compensation is applied during a subsequent fourth cycle in BB buck mode. First control signal in this transition924used to hold a reset on the capacitor for a period of time so that the charge on the capacitor is removed from the second slope compensation. As a result, the next fourth cycle starts with a lower voltage930. Use of control signals924,926, an error in the CSA output can be undone to preserve Vout904through a mode transition.

FEIGE.10is a flowchart of a method1000in at least one embodiment, control a slope compensation circuit to eliminate an error caused by a transition between a first mode and a second mode. method1000can be performed by processing logic that includes hardware, firmware, or a combination thereof. method1000can be run through a USB controller200vonFEIGE.2. In another embodiment, method1000can be performed by a slope compensation circuit204. In another embodiment, method1000can be done through a USB Type-C controller600vonFEIGE.6.

I refer back toFEIGE.10, Method1000Starts with processing logic that detects a transition of a buck-boost converter from a first mode with a first duty cycle to a second mode with a second duty cycle less than the first duty cycle (block).1002). The processing logic provides an output based on an input current and a slope compensation current (block1004). The output contains an error caused by the transition. The processing logic drives an offset output to eliminate the error caused by the transition (block).1006) and method1000ends.

In another embodiment where the first mode is a BB buck mode, the processing logic causes a charge to be stored on a capacitor during a first BB cycle. The processing logic causes the charge to be applied during a second BB cycle to start the second BB cycle at a higher voltage than the first BB cycle.

In another embodiment where the first mode is a BB gain mode, the processing logic disables slope compensation during a first BB cycle and enables slope compensation during a second BB cycle following the first BB cycle. In one embodiment, the processing logic causes a capacitor to store slope compensation during the first BB cycle, but removes the slope compensation so that it is not applied during the second BB cycle.

In one embodiment, processing logic can detect a transition by measuring an output voltage (Vout) and an input voltage (Vin). The processing logic may determine that the transition from a BB gain mode to a BB buck mode occurs when the input voltage (Vin) reaches or exceeds a first threshold associated with Vin approaching Vout. In another embodiment, the processing logic may determine that the transition from a BB buck mode to a BB boost mode occurs when the output voltage (Vout) reaches or exceeds a second threshold associated with Vout. Vin approaches.

The following embodiments relate to an IC controller that includes a controller coupled to an edge compensation circuit, the controller causing the edge compensation circuit to apply a first edge compensation to the input current in a first mode in which the buck boost converter operates to are used in a DCM. The controller detects a transition of the buck-boost converter from a first mode with a first duty cycle to a second mode and causes the edge compensation circuit to apply a second edge compensation to the input current. The second slope compensation starts at a maximum offset of the first slope compensation. Using the slope compensation component, the same EA voltage can be maintained by adding an offset to the CSA output using slope compensation using a programmable slope percentage per mode, a programmable delayed start of slope compensation , or both. This reduces the amount of movement EA needs with each mode transition. To reduce EA movement, the tilt compensation component is dynamically changed in each mode to reduce EA movement. For example, the tilt compensation component can be turned on after a delay (Td) after a reset (PWM reset). The slope compensation component moves with the PWM, helping to maintain the same EA output voltage. By delaying the tilt compensation component, the offset is added based on the amount of time the switch is on. In addition, the tilt compensation component to be added and the delay for which tilt compensation is turned off are programmable and can be used to further minimize EA's motion. Details of these embodiments are described below with respect to FIGAFB.11-15. It should be noted that the above-described embodiments of the compensation circuit with respect toAFB.2,6-7apply to the embodiments ofAFB.16-21.

FEIGE.11is a time map1100a slope compensation signal1102containing a slope compensation component1104in a cycle is delayed by a programmable amount1106(Td) in at least one embodiment. It also shows a CSA_OUT signal1108with slope compensation component1104added to the CSA signal1110which indicates the inductor current (iL).1112. Starting a slope compensation component from the previous cycle allows CSA_OUT to start at a higher offset voltage, as indicated by1114instead of starting with a lower voltage1116at the beginning of each shift cycle. This additional compensation1114helps keep EA at the same voltage for subsequent cycles in the second mode after a mode transition from the first mode to the second mode. A programmable delay (Td)1106can be used in different modes to provide different offsets1114in the different modes that can help keep an EA at the same voltage across multiple modes along with a method to cancel errors in the CSA output (e.g. CSA_OUT) by adding or removing offset during the mode transition .

In other embodiments, the tilt compensation component can be started from a previous cycle to continue adding the same tilt compensation offset to prevent EA movement, as illustrated in FIG.FEIGE.12.

FEIGE.12is a time map1200a slope compensation signal1202This starts the tilt compensation of a previous cycle1204to continue adding the same tilt compensation offset1206to avoid motion of an error amplifier output (EA) in at least one embodiment. In a mode transition between a first mode (e.g. BB-buck mode) and a second mode (e.g. BB-boost mode), the slope compensation of the previous cycle takes place1204The cycle of the first mode is transferred to the first cycle of the second mode to prevent EA movements from the first mode to the second mode. In the second mode, tilt compensation is started from the previous cycle1212(after programmable Td delay as shown inFEIGE.11) to start CSA from an offset voltage1214at the start of the next cycle. This addition of slope compensation from a previous cycle occurs for each subsequent cycle of the second mode. This helps to keep the EA in the second mode (e.g. BB boost mode) at the same level in all cycles. Similar addition of the tilt compensation component occurs in all modes, as shown in FIG1216,1220, In1208This helps to start each cycle of each mode with an offset1218,1222, In1210in the respective modes. In at least one embodiment, the offset introduced by the slope compensation component in each cycle is always the same when the slope compensation component itself was started in the previous cycle. This helps keep EA (and Vout) stable without the need for sample-and-hold circuitry with regular updates across all buck-boost modes. The offset is only changed at the mode transition limits to accommodate a sudden duty cycle change.

Adding the same tilt compensation offset can improve low current operation in the DCM. That is, adding the same slope compensation offset to each cycle can improve the Vout ripple, as shown in two separate waveform diagramsAFB.13A-13B. In addition, a skew compensation percentage and a skew compensation start delay (scap_rst width) are programmable to change the skew compensation offsets. Because the slope compensation percentage and ramp-up time are programmable, there are many alternative schemes by which to tune this system to achieve better performance (ripple, response time) based on Vin/Vout/Load combinations.

FEIGE.13Ais a time map1300an output voltage (Vout)1302Use of a first tilt compensation scheme in at least one embodiment. i g.13B is a timetable1320an output voltage (Vout)1322Using a slope compensation schedule that, in at least one embodiment, starts slope compensation from a previous cycle. As shown inFEIGE.13Athe programmable delay Td can be programmed to convert the schedule to a conventional ramp compensation schedule where no ramp compensation component is added in the previous cycle and ramp compensation starts from the start of the next cycle. As shown inAFB.13BThe slope compensation component has been added from the previous cycle and shows better overshoot/undershoot in Vout1322compared to Vout1302InFEIGE.13Ain DCM mode.

As described above, a mode-based tilt compensation percentage is programmable, as shown in FIGAFB.14A-14B.

FEIGE.14Ais a time map1400an output voltage (Vout)1402Use of different programmable slope compensation percentages per mode in at least one embodiment. In this embodiment, a first tilt compensation percentage (e.g. 80%) is programmed for a buck mode, a second tilt compensation percentage (e.g. 70%) is programmed for a BB buck mode, a third tilt compensation percentage (e.g. 200%) is programmed for a boost mode , and a fourth tilt compensation percentage (e.g. 150%) is programmed for a BB boost mode. A different tilt compensation percentage can be programmed for each mode to minimize EA movement during the mode transition.

In addition, the tilt compensation can be programmed to have a different start delay for each mode. Fixed or variable slope compensation percentages allow slope compensation to be added after a programmable delay in the previous cycle. This can help provide a combination of schedules for each mode. For example, a fixed (1×) slope compensation can be activated from the start of a shift cycle. This is perhaps best suited to a buck mode and can offer the benefit of much longer response time and lower ripple. The other modes can be programmed with different delays, slope compensation percentages, or both. An example of a programmable delay mode is shown in FIGFEIGE.14B.

FEIGE.14Bis a time map1420an output voltage (Vout)1422Using a programmable delay in one of several modes of a buck-boost converter in at least one embodiment. For example, a fixed ramp compensation can be activated with a delay from the first Td (e.g. 50% of the shift cycle) for the buck and BB buck modes, and the same or a different fixed ramp compensation can be activated with a Delay activated from the second Td (e.g. 10% of shift cycle) for Boost and BB Boost modes.

In an alternate variation of the same scheme, called the delayed boost scheme, there are three modes: buck mode, buck-boost mode, and boost mode. The duty cycle transitions smoothly from buck mode to buck-boost mode, eliminating the need for abrupt EA movements. The duty cycle from buck-boost mode to boost mode must be changed from 85% to 15%, which can cause the EA to abruptly change to boost mode. In boost mode, a boost charge cycle is delayed by 70% from the start of the shift cycle when the mode transitions from buck-boost mode to boost mode. Therefore, the slope compensation current is integrated to a value of 85%, which is similar to the buck-boost mode. This boost start delay further decreases as the Vin/Vout ratio decreases, so that the required boost duty cycle is achieved when the deep boost converter enters a deep boost mode.

FEIGE.15is a flowchart of a method1500in at least one embodiment applying a second tilt compensation starting at an equal or different (programmable) offset of a first tilt compensation. method1500can be performed by processing logic that includes hardware, firmware, or a combination thereof. method1500can be run through a USB controller200vonFEIGE.2. In another embodiment, method1500can be performed by a slope compensation circuit204. In another embodiment, method1500can be done through a USB Type-C controller600vonFEIGE.6.

I refer back toFEIGE.15, Method1500starts with the processing logic applying first slope compensation to an input current of a buck-boost converter in a first mode where the buck-boost converter is operating in a DCM (block).1502). The first mode has a first duty cycle. The processing logic detects a transition of the buck-boost converter from the first mode to a second mode with a second duty cycle less than or greater than the first duty cycle (block1504). The processing logic applies a second slope compensation to the input stream (block1506), where the second tilt compensation starts at an equal or different (programmable) offset from the first tilt compensation, and the method1500ends.

In another embodiment, the processing logic detects a transition from a BB buck mode to a BB boost mode. In this embodiment, the first slope compensation includes a first slope percentage and the second slope compensation comprises a second slope percentage that differs from the first slope percentage.

In another embodiment, the processing logic in a third mode applies a third slope compensation to the input current. The third tilt compensation includes a third tilt percentage that is different from the first tilt percentage and the second tilt percentage. The third mode can be a buck mode or a boost mode or a BB buck mode or a BB boost mode.

In another embodiment, the processing logic delays a first delay amount (or delay time) before applying the first slope compensation and delays a second delay amount (or delay time) before applying the second slope compensation, the first delay amount, and the second delay amounts. are different. The amount of delay can be a period of time, a specific time interval, a time value of a timer, or the like. In another embodiment, the first tilt compensation and the second tilt compensation each contain a fixed tilt percentage. In another embodiment, the first tilt compensation and the second tilt compensation comprise a variable tilt percentage.

In another embodiment, the processing logic slows down from the start of a shift cycle before applying the second ramp compensation by a delay amount, where the delay amount is a specified percentage of the shift cycle.

The following embodiments are directed to an IC controller that includes a digital control offset mode as described below with respect to FIGAFB.16-20. It should be noted that the above-described embodiments of the compensation circuit with respect toAFB.2,6-7apply to the embodiments ofAFB.16-20. A buck-boost converter enters a hopping mode, also known as pulse skipping mode (PSM), when the power delivered in a cycle with a minimum PWM on time exceeds a required load. The buck-boost converter converts the buck-boost switches one cycle. Once in skip mode, it does not flip switches and waits until it exits skip mode before flipping switches. The frequency of the operation varies in switch mode because some cycles are skipped between entering and exiting jump mode. A transition from CCM to DCM and vice versa requires large swings in the EA output to minimize undershoot or overshoot. In jump mode, the EA output goes to a very low voltage and any sudden load change requires a large EA movement, resulting in a large drop in Vout.

In a conventional scheme for DCM, at the beginning of each clock cycle, the switch is turned on and the inductor current (iL) builds up. This stream is detected by CSA and CSA produces an output called the CSA output. Tilt compensation is the part to be added for current mode instability. CSA components and slope compensation components are added each cycle as CSA output and compared to EA output. When the CSA output reaches the EA level, a control signal (PWM) switches, resetting the switch and causing the inductor current to decrease and reach zero in the DCM. In every DCM cycle, there is a dead time where the inductor current is zero. In the next clock cycle, the switch turns back on and this process repeats. With the conventional scheme, at any mode transition from CCM-DCM or DCM-Skip, the required motion in EA is very high and results in the output falling or exceeding in Vout, which does not meet the USB-PD specification requirements. Due to the tilt compensation component, EA can be a very slow moving signal. For an inductor rating, the output voltage EA is an indication of the power required by the inverter. The higher the voltage, the higher the output power, as the on-time increases with increasing EA power. By using the slope compensation component in the trip time, the same EA voltage can be maintained since using the slope compensation adds an offset to the CSA output. This can reduce the motion required by EA when there is a mode transition between CCM and DCM.

To reduce EA movement, a scheme can be used where the tilt compensation component is dynamically changed each cycle to reduce EA movement. Instead of leaving the slope compensation inactive after the PWM reset, the slope compensation can be enabled after a delay (Td) after the PWM reset. The slope compensation component moves with the PWM, helping to maintain the same EA output voltage. As shown inFEIGE.11, the slope compensation starts with a Td delay and dynamically adds the offset based on the length of time the switch is turned on. In addition, the tilt compensation component to be added and the delay for which tilt compensation is turned off are programmable and can be used to further minimize the motion of the EA.

In the embodiments described below, different architectures are described to avoid the need for large EA moves during load-based mode transition, i.e. H. from CCM to DCM, which can then meet +/-5% Vout and monotonicity requirements over a wide range to input and output ranges. The skip mode architecture can be implemented to ensure that the buck-boost converter enters and exits skip mode based on output power demand and that no movement is required at the EA level.

FEIGE.16Figure 12 is a block diagram of a USB controller1600with analog and digital skip mode in at least one embodiment. USB controller1600resembles a USB controller200vonFEIGE.2, except the USB controller1600Includes a skip mode comparator1602receiving a skip mode reference1601and an EA signal1603by EA208. Jump mode comparator1602can generate a skip mode signal1605This is fed into the BB control logic210. A skip mode can be entered and exited via the skip mode comparator1602Comparison of EA signal1603(comp_out) (a GM amp output) to skip the mode reference1601. As shown in a timing diagram1700vonFEIGE.17A, as an EA signal1603(comp_out) is higher than the jump mode reference1601by a certain voltage, skip mode comparator1602Exit1605remains low and enables the set_buck signal1607and/or set_boost signal1609consist of. When the EA signal1603lower than the jump mode reference1601, Sprungmode comparator1602Exit1605goes up and does not allow set_buck to be passed1607and set_boost1609signals. As described here, EA signal1603(comp_out) is a voltage that is compared by the comparator206to compensate for the CSA signal205, including slope compensation component.

Each buck-boost converter must turn the switches on and off to maintain the duty cycle. Since the switch takes a finite amount of time to turn on and off, there is a minimum duty cycle and maximum duty cycle achievable with the buck-boost converter. When the required duty cycle is less than the minimum possible for a buck-boost converter, it enters hopping mode, in which the buck-boost converter switches at the minimum duty cycle for one cycle and does not switch on subsequent cycles, effectively reduce and thus reduce frequency The duty cycle reaches the minimum achieved by the inverter. When the buck boost converter enters skip mode it can remain in skip mode for tens of milliseconds during which EA can drop to a very low level and with each increase in load current EA takes longer to return to its previous value range, which can cause major undershoot problems at the output. In addition, the minimum value of EA varies depending on the mode required for skip mode, making it much more difficult to correctly define skip mode. It can be difficult to accurately determine the skip mode reference1601for the skip mode as the tilt compensation offset is added to the CSA signal205is different in different modes. These components must be carefully designed to accurately predict jump references for entering and exiting a jump mode. Offset CSA signal205can vary greatly depending on the mode and it can be difficult to implement skip mode with this approach.

To overcome the shortcomings described above, the module PWM_OUT1611The pulse can be digitally compared to a minimum pulse width by BB control logic210to skip boarding or disembarking. PWM_OUT1611The pulse is generated by comparing the CSA_OUT signal205with comp_out signal1603with comparator206. Als PWM_OUT1611The pulse has a width greater than a minimum jump ON time, after which a controller exits jump mode and passes through PWM_OUT1611Signal a set_buck1607and/or set_boost1609Signal dependent on buck-boost mode. If PWM_OUT1611If the pulse has a width less than a minimum hop ON time, which means that less power must be delivered than the minimum power in DCM mode, the controller switches to hop mode and does not pass PWM_OUT1611Signal a set_buck1607and set_boost1609signals. Skip-ON time can be programmed to support different applications and optimize efficiency in low power mode. A programmable digital hysteresis can be added between the ON time thresholds for the skip input and skip output pulse widths to ensure no chatter occurs. In this embodiment, no analog block is required to implement the skip mode. This can reduce design complexity. Since a clock signal can be very accurate (e.g. +/-2%) and the resolution of the skip mode is determined by a clock period (e.g. 20 ns, 40 ns or similar), the skip mode is also In- and exit can be accurately predicted and controlled.

FEIGE.18is a time map1900Illustrating signals during a jump mode in at least one embodiment. timetable1900shows entering and exiting a skip mode along with the operation of a buck-boost converter. In conventional mode, the jump mode is based solely on the absolute EA voltage, as shown inFEIGE.17. EA-spanning1902(which is the same as comp_out1603InFEIGE.16) is a derivative of an output voltage Vout. CSA_OUT signal205is compared to the EA voltage1902to the generated PWM1906Signal. CSA_OUT signal205is the combined signal of CSA1908and slope comp1904Signal. The width of PWM1906The signal is digitally compared to a predefined SKIP input width threshold in the BB control logic210to decide whether the part should go to SKIP mode or not. If the width of PWM1906Signal is less than SKIP input width threshold, digital SKIP1910The signal is activated and the buck-boost converter switches to SKIP mode. The situation is similar to the width of the PWM1906greater than the SKIP output width threshold, then digital SKIP1910The signal is turned off and the low-boost converter exits SKIP mode. In skip mode, the buck-boost converter does not pulse the drivers via the set_buck/set_boost signals212In214There is no inductor current (iL) and no CSA signal1908. Therefore in SKIP mode EA voltage1902is compared to a CSA_OUT signal205This is the same as slope compensation1904to generate a PWM pulse1906even though the device goes into skip mode. In this scheme, a pulse width duration can be used to determine the arming and disarming mode. Switching the skip mode on and off is based solely on the pulse width, which encodes information about the direction of movement of Vout. If the required output power is lower, PWM is used1906The pulse width becomes small, and when the duration of the pulse width becomes less than the step input threshold, the buck-boost converter is controlled to enter step mode. In skip mode, the EA output is compared to the slope compensation and a pulse is generated whose duration is compared to the skip output threshold. When this pulse width reaches the skip exit threshold, the buck-boost converter is controlled to exit skip mode.

As shown inFEIGE.19, in a first cycle1912bicycle1The buck-boost converter is controlled to operate in DCM mode and the duration of the PWM pulse width exceeds a step threshold, so the device operates in DCM mode and with a step signal1910is set to 0. In a second cycle1914, bicycle2, the width of the PWM pulse is less than the step input threshold, so a step signal1910is set and the unit switches to skip mode. In a third cycle1916, bicycle3, the device is in skip mode and all switches are off and CSA output1908is 0. A tilt compensation component1904is compared to the EA voltage1902to generate a PWM pulse1906. The width of the PWM pulse is smaller than the skip output threshold and continues in the skip mode. In a fourth cycle1918, bicycle4, the PWM pulse width is greater than a skip output threshold and the device removes (or resets) the skip flag (skip signal).1910is set to 0). In a fifth cycle1920, bicycle5, the device works in DCM and the PWM pulse width is lower than the jump input threshold and the jump signal1910is set. In a sixth cycle1922, the device is in skip mode and all switches are off and CSA output1908is 0. A tilt compensation component1904is compared to the EA voltage1902to generate a PWM pulse1906. The PWM pulse width is smaller than the skip output threshold and still in the skip mode and the skip signal1910continue high.

FEIGE.19is a flowchart of a method2000digital control of a jump mode in at least one embodiment. method2000can be performed by processing logic that includes hardware, firmware, or a combination thereof. method2000can be run through a USB controller200vonFEIGE.2. In another embodiment, method2000can be performed by a slope compensation circuit204. In another embodiment, method2000can be done through a USB Type-C controller600vonFEIGE.6. In another embodiment, method2000can be executed by the BB control logic210vonFEIGE.2InFEIGE.16.

I refer back toFEIGE.19, Method2000starts on a first edge (for example, a positive edge) of a clock block2002by processing logic that zeroes a capacitor reset indicator and zeroes a CSA reset indicator (block2004). The processing logic determines whether a second edge (e.g. negative edge) of a PWM pulse is detected (block2006). When the edge of the PWM pulse on the block is detected2006, the processing logic sets the capacitor reset indicator to one (block2008). The processing logic initiates a programmable delay (Td) and determines if the pulse width of the PWM pulse is below a jump threshold at the block2012. When the pulse width is smaller than the block input skip threshold2012, the processing logic sets a skip mode indicator to one and the CSA reset indicator to 1 at the transition to the block2010to determine if the programmable delay (Td) has elapsed. If not, the processing logic returns to the block2008. When on the block2010If the processing logic determines that the pulse width is not smaller than the jump input, the processing logic zeroes the jump mode indicator at the block2016and go to block2010to determine if the programmable delay (Td) has elapsed. Once the programmable delay (Td) has elapsed, the processing logic enters the block2018to zero the capacity reset indicator and enter the block2020At this point, the processing logic determines whether the jump mode indicator is set to 1. If so, the processing logic returns to the block2006. If the jump mode indicator is not set to 1, the processing logic returns to block2020waits for a first edge (e.g. positive edge).

In another embodiment, instead of measuring the pulse width over one cycle to detect the hopping mode, the pulse widths can be averaged over multiple cycles to remove any PWM interference. In another embodiment, the dead time after which ramp compensation begins may be programmable and vary from cycle to cycle. In another embodiment, the slope compensation components added during the switch on and off times may be different and changed to minimize the ripple in Vout. In another embodiment, the dead time and edge compensation components added during the switch's on and off times can be changed in each cycle to achieve a fixed offset, making it independent of small signal noise in the PWM.

In one embodiment, the mode transition architecture can be used for any buck-boost converter in a USB PD application. In another embodiment, the mode transition architecture for each buck-boost converter can be used in other applications. In another embodiment, the mode transition architecture can be used in gain converters. In another embodiment, the mode transition architecture can also be used in other power converters.

The mode transition architecture embodiments described herein can provide a simpler architecture with less design complexity. Control logic implementing the mode transition techniques described herein can be implemented in circuits using Register Transfer Level (RTL). Mode transition architecture implementations can also have a small chip area. Embodiments of mode transition architectures can operate seamlessly between CCM and DCM mode operation. Implementations of mode transition architectures can allow for lower load capacitance, as there is less IO movement and a capacitor is required to support the load current during this time, reducing the amount of capacitance, the bill of material (BOM) cost, and space requirement on a plate be lowered. In some embodiments, firmware can be used to change a scheme in different converter modes. Firmware can provide programmable options to tune each mode based on customer specific operating modes, e.g. B. buck only modes or boost only modes and even older modes of operation. Firmware provides flexibility in using the IC controller in different applications, programmability and fast design time for implementing the IC controller in a new application. Implementations of the digital skip mode architecture can reduce the accuracy requirements of the CSA and tilt compensation blocks. This also reduces design complexity by providing simpler block components, smaller die area and lower power consumption. In addition, the digital skip-mode architecture as described here can be very accurate, as the accuracy depends on the clock frequency (e.g. 24 MHz), which can be easily achieved in terms of performance. A digitally controlled input skip threshold can be programmable to achieve optimum efficiency in a power saving mode for different applications. This can provide scalability and programmability in different applications.

FEIGE.20Figure 12 is a block diagram of an on-die IC controller2100with a USB PD subsystem in at least one embodiment. IC controller2100Figure 1 is an example of a semiconductor device configured according to the USB-C mode transition architecture described herein. In the illustrated versionFEIGE.20, IC-controller2100is a single-chip IC controller fabricated on a semiconductor chip. For example IC controller2100may be a single-chip IC device from the CCGxx family of USB controllers developed by Cypress Semiconductor Corporation of San Jose, California. In another example an IC controller2100may be a single-chip IC manufactured as a system-on-chip (SoC). In other embodiments the IC controller2100may be a multi-chip module encapsulated in a single semiconductor package. Including IC controllers2100Contains the Central Processing Unit (CPU) subsystem.2102, peripheral connection2114, system resources2116, input/output (I/O) subsysteem2118, USB-PD subsystem2120and various connectors (e.g. pins) configured to receive and transmit signals.

CPU-subsystem2102contains one or more CPUs2104, Flash memory2106, SRAM (static random access memory)2108en ROM (Read Only Memory)2110associated with the system connection2112. CPU2104is a suitable processor that can be used in an IC or a SoC device. Flash memory2106is non-volatile memory (e.g., NAND flash, NOR flash, etc.) configured to store data, programs, and/or other firmware instructions. Flash memory2106is closely related to the CPU subsystem2102for improved access times. SRAM2108is volatile memory configured to store data and firmware instructions that the CPU can access2104. Rom2110is read-only memory (or other suitable storage medium) configured to store boot routines, configuration parameters, and other firmware parameters and settings. system connection2112is a system bus (e.g., a single-tier or multi-tier Advanced High-Performance Bus, or AHB) configured as an interface that links the various components of the CPU subsystem2102each other and as a data and control interface between the various components of the CPU subsystem and the peripheral link2114.

peripheral connection2114is a peripheral bus (for example, a single-level or multi-level AHB) that provides the primary data and control interface between the CPU subsystem2102and its peripherals and other resources, such as B. System resources2116, E/A subsystem2118and USB PD subsystem2120. The peripheral connection2114may include various controller circuits (e.g., direct memory access or DMA controllers) that can be programmed to transfer data between peripheral blocks without burdening the CPU subsystem2102. In various embodiments, each of the components of the CPU subsystem and peripheral connection may vary depending on the choice or type of CPU, system bus, and/or peripheral bus.

system resources2116consist of various electronic circuits that support the operation of the IC controller2100in its various states and modes. For example system resources2116may contain a power subsystem with analog and/or digital circuitry required for each state/mode of the controller, such as sleep control circuitry, wake-up interrupt controller (WIC), power-on-reset (POR), voltage and/or or current reference circuits (REF), etc. In some embodiments, the power subsystem may also contain circuits that allow IC control2100to generate and/or supply power from/to external sources at multiple different voltage and/or current levels and to support controller operation in multiple power states2117(e.g. active state, sleep state and deep sleep state with clocks off). In addition, in some embodiments, the CPU subsystem2102can be optimized for power-efficient operation with extended clock ports and can include several internal controller circuits that allow the CPU to operate in different power states2117. For example, the CPU may include a wake-up interrupt controller configured to wake the CPU from a sleep state, allowing power to be turned off when the IC chip is in a sleep state. system resources2116may also include a clock subsystem having analog and/or digital circuitry for clock generation and clock management, such as clock control circuitry, watchdog timer circuitry (WDT), and internal low-speed oscillator circuitry (ILO). ) and internal main oscillator circuit(s), etc. System resources2116May also include analog and/or digital circuit blocks that provide reset control and support remote reset (XRES).

In various versions, I/O subsystem2118may contain different types of I/O blocks and subsystems. For example in the illustrated versionFEIGE.21, E/A subsystem2118Contains GPIO (General Purpose Input Output) blocks.2118A, the TCPWM block (timer/counter/pulse width modulation).2118Band SCBs (serial communication blocks)2118C. GPIO's2118Ainclude analog and/or digital circuitry configured to implement various functions such as pull-ups, pull-downs, input threshold selection, input/output buffer toggles, multiplexed signals connected to different I/O O pins, etc. TCPWMs2118Binclude analog and/or digital circuits configured to implement timers, counters, pulse width modulators, decoders, and various other analog/composite signal elements configured to operate on input/output signals. SCBs2118Cinclude analog and/or digital circuits configured to implement various serial communication interfaces such as I2C, SPI (serial peripheral interface), UART (universal asynchronous receiver/transmitter), CAN interface (controller area network), and CXPI (clock extension). peripheral interface), etc.

USB-PD subsystem2120Provides the interface to a USB Type-C connector and is configured to support USB communication and other USB functions such as power delivery and battery charging. USB PD subsystem2120Contains the electrostatic discharge (ESD) protection circuitry required for a Type-C connector. USB PD subsystem2120Also includes a Type-C transceiver and physical layer logic (PHY) configured as a baseband PHY integrated circuit to perform various digital encoding/decoding functions (e.g. Biphase Mark Code-BMC encoding/decoding, cyclic redundancy checks-CRC, etc. ) and analog signal processing functions involved in physical layer transmissions. USB PD subsystem2120also provides the terminating resistors (RP and RD) and their switches as required by the USB PD specification to implement connection sensing, connector orientation sensing, and power delivery functions over a Type-C cable. IC controller2100(and/or the USB PD subsystem2120thereof) can also be configured to respond to communications defined in a USB PD specification, such as Start-of-Packet (SOP), SOP′, and SOP″ messages.

Including the USB PD subsystem2120may also include: one or more analog-to-digital converters (ADCs) for converting various analog signals to digital signals; a VCONN FET; an error amplifier (ERROR AMP) for controlling the current source voltage applied to the VBUS line according to a PD contract; a high voltage regulator (HV REG) to convert the supply voltage to the exact voltage (e.g. 3-5V) required by the IC controller2100; a current sense amplifier (CSA) and overvoltage protection circuit (OVP) to provide overcurrent (OCP), overvoltage (OV), and undervoltage (UV) protection on the VBUS line with configurable thresholds and response times; a pulse width modulator (PWM); one or more gate drivers (GATE DRV) to control the power switches that turn the power on and off over the VBUS line; a low-side gate driver (LSDR), a high-side gate driver (HSDR) for controlling switches of the buck-boost converter; communication channel PHY logic (CC BB PHY) to support communication on a Type-C communication channel line (CC); a load protocol detection block (CHG DET) to detect different types of PD loaders; and at least two on-chip discharge circuits (VBUS DISCH) capable of discharging a VBUS line voltage to any programmable voltage level.

Different implementations of the USB-C mode transition architecture described herein may involve different operations. These operations can be performed and/or controlled by hardware components, digital hardware and/or firmware and/or combinations thereof. As used herein, the term "linked to" can mean linked directly or indirectly through one or more intermediate components. Each of the signals delivered over different on-chip buses can be time-multiplexed with other signals and delivered over one or more common on-die buses. In addition, the connection between circuit components or blocks can be represented as buses or as separate signal lines. Each of the buses may alternatively be one or more individual signal lines, and each of the individual signal lines may alternatively be buses.

Certain embodiments may be implemented by firmware instructions stored on a non-temporary computer readable medium, e.g. B. a volatile memory and/or a non-volatile memory. These instructions can be used to program and/or configure one or more devices, including processors (e.g., CPUs) or equivalents thereof (e.g., processing cores, processing engines, microcontrollers, and the like), so that they run when executed by the processor(s). ) or their equivalent, the instructions cause the device(s) to perform the operations described for the USB-C mode transition architecture described herein. The non-temporary computer readable storage medium may include, but is not limited to, an electromagnetic storage medium, read-only memory (ROM), random access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or a other now known or later developed non-volatile medium suitable for storing information.

Although the operations of the circuit(s) and blocks are shown and described herein in a particular order, in some embodiments the order of the operations of each circuit/block may be rearranged so that certain operations can be performed in the reverse order or so that certain operations operations can be performed at least partially simultaneously and/or in parallel with other operations. In other embodiments, instructions or sub-operations of different operations may be executed intermittently and/or alternately.

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.